1. Field of the Invention
The present invention relates to the field of three dimensional integrated circuits and more specifically, to a method for forming a coupled wafer pair that prevents edge chipping.
2. Discussion of Related Art
In the manufacture of microelectronic devices, packaging density is becoming increasingly important. Stacking of the dice of a multi-processor microelectronic device is one way to improve the packaging density of a microelectronic device. Stacked microelectronic devices are typically formed by electrically connecting two or more wafers through interconnect layers, and then dicing the stacked wafers into individual stacked devices.
FIGS. 1A–1D illustrate one method for forming a coupled wafer pair. As shown in FIG. 1A, a first wafer 101 and a second wafer 102 are provided. Typically, these wafers are silicon polycrystalline wafers which have a plurality of die that are connected together. Typically, each die is an integrated circuit. Next, as shown in FIG. 1B, an interconnect layer 103 is formed on the first wafer 101 and on the second wafer 102. The interconnect layer 103 is typically copper that is formed above a barrier material such as tantalum and a dielectric layer such as silicon dioxide or carbon dioxide. Typically, there are hundreds of copper members in the interconnect layer 103.
Next, as shown in FIG. 1C, the first wafer 101 and its associated interconnect layer 103 is flipped around and positioned over the second wafer 102 and its interconnect layer 103. Next, in FIG. 1D, a coupled wafer pair 100 is formed by aligning the interconnect layers 103 of the first wafer 101 and the second wafer 102 and bringing the first wafer 101 and the second wafer 102 together. Typically a thermo-compression process is used to couple the first wafer 101 with the second wafer 102.
Typically, as shown in FIG. 1D, thinning 107 of one of the stacked wafers is performed by use of one or more mechanical and/or chemical processes such as a polishing process for example. These processes may cause mechanical stresses in unsupported portions of the wafer being thinned. As shown in an outer gap 106, an area formed by the product of a depth 105 and a height 104 is unsupported by the interconnect layer 103. Furthermore, a center gap 108 between individual members of the interconnect layer 103 may also be unsupported.